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NVIDIA

Jetson compute, Isaac & GR00T

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HUMANOID ROBOT

Where it fits in the robot

Jetson Thor hardware, Isaac simulation, and GR00T foundation models form a connected robotics development stack, spanning training through deployment.

What the evidence establishes

Humanoid evidence

Jetson Thor and the Isaac/GR00T stack explicitly target humanoids, with named robot developers. NVIDIA is not a DRAM or standalone heat-sink manufacturer.

An explicit humanoid product, development program, application, or partnership. This does not establish revenue, market share, or production volumes.

Component roleJetson compute, Isaac & GR00T
EvidenceJetson Thor and the Isaac/GR00T stack explicitly target humanoids, with named robot developers. NVIDIA is not a DRAM or standalone heat-sink manufacturer.
Primary sourceNVIDIA — supporting disclosure
Company or official disclosure; vendor claims are attributed to their source.
Checked. This is the research review date, not the source publication or quote time.

Keep in perspective

Robotics is a small, unseparated part of a much larger AI computing business. Adoption is not a humanoid revenue forecast.

Platform business exposure. This describes the breadth or role of the business; it is not an investment rating. A robotics product or development announcement does not by itself establish material humanoid revenue, market share, or future returns.

Connections to the assembly

These links explain the technology relationship. The model is illustrative and does not represent an actual manufacturer’s bill of materials.

Compute carrier board

The circuit board routes power and high-speed signals between compute, memory, and peripherals.

Scope of the company links: Compute modules and reference platforms, plus board interconnects (Amphenol) and power electronics (MPS). Not bare-PCB fabrication.

AI & control processor

The main processor executes perception and planning. Real-time control can run on separate processing cores or devices.

Scope of the company links: AI processors and embedded real-time controllers serve different workloads. Arm licenses processor IP; it does not manufacture chips.

AI SERVER RACK

Where it fits in an AI server rack

Designs the GB300 NVL72 rack-scale platform: 72 Blackwell Ultra GPUs and 36 Grace CPUs (2,592 Arm Neoverse V2 cores), 20 TB of HBM3E, 130 TB/s of NVLink bandwidth, ConnectX-8 SuperNICs and Quantum-X800 InfiniBand or Spectrum-X Ethernet; its DGX GB300 adds 18 BlueField-3 DPUs and 9 NVLink Switches. Each Blackwell GPU has 208 billion transistors on two reticle-limited dies built on a custom TSMC 4NP process. Vera Rubin was ramping into full production in Q2 FY2027 (quarter to July 26, 2026), when Data Center revenue was $89.0B.

What the evidence establishes

AI-rack evidence

Disclosed: NVIDIA’s GB300 NVL72 and DGX GB300 pages give the GPU, CPU, NVLink, ConnectX-8, BlueField-3 and NVLink Switch counts, and its FY2026 10-K names its foundry, memory and assembly partners.

An explicit AI-server or AI-rack product, design-in, supply role, program, reference design or partnership, such as a part named for rack-scale AI systems or a product sold for AI data centers. For a rack builder, it means the company’s own AI servers or racks. This does not establish revenue, market share, volumes or future sourcing.

Listed as a rack builder for its own AI servers and racks, not as a supplier of the parts inside.

Component roleBlackwell GPUs, Grace CPUs, NVLink and the NVL72 platform
EvidenceDisclosed: NVIDIA’s GB300 NVL72 and DGX GB300 pages give the GPU, CPU, NVLink, ConnectX-8, BlueField-3 and NVLink Switch counts, and its FY2026 10-K names its foundry, memory and assembly partners.
How we knowDisclosed The company’s own filing, release, annual report, product page or investor record describes the AI-server or AI-rack role. Where customers are unnamed, the listing says so.
Primary sourceNVIDIA — supporting disclosure
Company or official disclosure; vendor claims are attributed to their source.
Checked. This is the research review date, not the source publication or quote time.

Keep in perspective

NVIDIA designs the chips and the platform; TSMC fabricates the dies and partners build the racks. Data Center revenue is not split by rack model, and the NVL72 is one of several system configurations.

Platform business exposure. This describes the breadth or role of the business; it is not an investment rating. An AI-server product, design-in or partnership does not by itself establish material AI-rack revenue, market share, or future returns.

Connections to the assembly

These links explain the technology relationship. The model is illustrative and does not represent an actual manufacturer’s bill of materials.

GPU compute dies

Two reticle-sized logic dies joined into one GPU, built on a leading-edge foundry process. They run the matrix math of training and inference. Custom accelerators designed by or for cloud companies are the main alternative.

Scope of the company links: The compute dies. NVIDIA designs Blackwell and Blackwell Ultra (208 billion transistors on two reticle-limited dies, custom TSMC 4NP) and AMD designs the Instinct MI350 and MI455X; NVIDIA discloses that TSMC fabricates Blackwell. Custom accelerators are the alternative: Broadcom co-develops OpenAI-designed accelerators and racks (its other XPU customers are unnamed), Marvell develops custom AI silicon for unnamed customers, and the design-service houses Alchip (an N3 accelerator for a North American cloud provider, from May 2026) and GUC (AI accelerator design support) disclose programs without naming customers. Intel’s Gaudi 3 is a merchant AI accelerator with no documented rack-scale deployment. Hyperscaler chip designers (Google TPU, AWS Trainium) are not mapped because they do not sell the chips as components. Samsung is named as an NVIDIA wafer foundry but not for Blackwell GPU dies, so it is not mapped here.

Superchip module board

The board that carries two GPU packages and one CPU with their power stages and high-speed connectors. It docks into the compute tray and its cold plates.

Scope of the company links: The superchip board carrying two GPU packages and one Grace CPU is an NVIDIA design (GB300 Grace Blackwell Ultra Superchip). Wistron builds GB300 superchip boards and AI servers in Texas (NVIDIA partner documents). Victory Giant makes the printed circuit boards for AI computing cards and GPU baseboards (its investor record, July 1, 2026), but no source names the fabricator of a specific rack-scale module board. NVIDIA’s 10-K names Hon Hai among contract manufacturers without saying which builds the module, so Hon Hai is listed under Builders, not here; Fabrinet’s disclosed role is optical. The module’s power stages sit under voltage regulators.

Host CPU

An Arm-based or x86 processor that runs the operating system, stages data and coordinates the GPUs. In rack-scale designs it shares a coherent high-bandwidth link with its GPUs.

Scope of the company links: NVIDIA’s Grace is the host CPU of GB200/GB300 NVL72: a GB200 rack has 36 Grace CPUs with 2,592 Arm Neoverse V2 cores (NVIDIA spec page). Arm licenses the Neoverse cores; in March 2026 it also launched its own AGI CPU silicon. x86 alternatives are AMD EPYC (18 Venice CPUs in AMD’s Helios rack) and Intel Xeon hosts in 8-GPU HGX-class servers. Montage’s Jintide x86 CPUs have no documented AI-rack role and are not mapped.

Switch ASICs

Scale-up switch chips that connect every GPU in the rack to every other GPU at full bandwidth. Other designs use Ethernet switch chips for the same job.

Scope of the company links: Scale-up and fabric switch chips. NVIDIA’s NVLink Switch chips sit in the 1RU switch trays of GB200/GB300 NVL72 (NVIDIA OCP contribution, Oct 15, 2024), and its Spectrum-6 Ethernet ASIC runs 102.4 Tb/s. Broadcom sells Ethernet switching silicon to hyperscalers and to makers of AI servers, switches and racks (FY2025 10-K); Cisco’s Silicon One G300 (102.4 Tb/s) powers its own systems; Astera Labs’ Scorpio X-Series is a scale-up fabric switch for up to 80 accelerators; Marvell’s 10-K lists Teralynx Ethernet switches of up to 51.2 Tb/s. Celestica designs AMD Helios’s scale-up switch trays on other companies’ silicon and is listed under the top-of-rack switch, not here.

SuperNICs & network cards

Network cards at 400 to 800 Gb/s, about one per GPU, that carry scale-out traffic over InfiniBand or Ethernet to other racks.

Scope of the company links: GB300 NVL72 gives each GPU 800 Gb/s through ConnectX-8 SuperNICs (NVIDIA product page); ConnectX-9 offers 1.6 Tb/s. Broadcom sells Ethernet NICs into AI data centers (FY2025 10-K), and AMD’s Pensando Pollara AI NICs are the alternative in AMD systems such as Helios. Some hyperscalers use in-house NICs (analyst reports), which are not listed products.

DPUs

Data processing units: network cards with their own processor cores that offload storage, security and virtualization from the host CPU.

Scope of the company links: NVIDIA’s BlueField-3 (400 Gb/s) and BlueField-4 (800 Gb/s) DPUs offload networking, storage and security; NVIDIA lists two BlueField-3 DPUs per GB200 compute tray. AMD’s Pensando DPUs are the alternative in AMD designs. Intel IPUs and Marvell OCTEON DPUs had no AI-rack evidence in our sources and are not mapped.

Top-of-rack switch

The rack’s own switch boxes. In the reference design they carry the management network for every tray, while scale-out traffic leaves through each tray’s network cards; other designs also aggregate data traffic here.

Scope of the company links: The rack’s own switches. In NVIDIA’s reference rack the in-rack switches carry the management network, and scale-out traffic leaves through each tray’s SuperNICs to leaf switches. NVIDIA’s Spectrum-X Ethernet switches (SN5000/SN6000) are its reference fabric, and Meta and Oracle said they would adopt them (Oct 13, 2025). Arista (7060 AI leaf, 7800R AI spine), Cisco (Nexus N9000/N9100 and G300 systems), Celestica (hyperscale 800G white-box switches) and Accton’s Edgecore (51.2 Tb/s AIS800-64D) sell Ethernet switches for AI clusters, and Foxconn Industrial Internet reports that its 800G-and-above switch shipments rose more than 13-fold in 2025. The operator decides which switch serves a rack.

Optical transceivers

Pluggable 800G and 1.6T modules that convert electrical signals to light and back for links that leave the rack.

Scope of the company links: 800G and 1.6T pluggable modules (OSFP) for the rack’s scale-out links. NVIDIA names Coherent, Eoptolink, Fabrinet and Innolight as pluggable-transceiver leaders (Mar 18, 2025). Innolight, Eoptolink and Accelink list 1.6T OSFP modules in their 2025 annual reports, Coherent and Lumentum describe 800G/1.6T modules in their 10-Ks, and AOI has a first 1.6T volume order of over $200 million from an unnamed hyperscaler. Fabrinet is a contract manufacturer (NVIDIA was 16.3% of FY2026 revenue), not a module brand. NVIDIA sells LinkX-branded optical transceivers without naming their makers. TFC supplies optical engines and passive parts that go inside modules, and Credo sells ZeroFlap optical transceivers. None of these sources gives volumes or says which system a given module ships into. Cisco ships 1.6T OSFP and 800G linear-drive optics with its Silicon One systems, and Luxshare lists 800G and 1.6T optical modules in small-batch supply.

QUANTUM COMPUTER

Where it fits in a quantum computer

Launched NVQLink on Oct 28, 2025, an open architecture that couples GPU servers to quantum controllers through its CUDA-Q platform, with 17 QPU builders and controller builders Keysight, Quantum Machines, Qblox, QubiC and Zurich Instruments as partners; NVIDIA quotes 400 Gb/s of GPU-QPU throughput and under 4 microseconds of FPGA-to-GPU-to-FPGA latency. Quantinuum used NVQLink and CUDA-Q to decode qLDPC codes in real time on its Helios processor with a 67-microsecond reaction time (Nov 17, 2025), and NVIDIA’s open Ising models (Apr 14, 2026) add AI decoding and calibration.

What the evidence establishes

Quantum-computing evidence

Disclosed: NVIDIA’s NVQLink releases and product page describe the GPU-to-controller architecture, its partners and latency, and Quantinuum’s real-time decoding demonstration.

An explicit quantum-computing product, design-in, supply role, program or partnership, such as a part sold for quantum computers or a named quantum-computer customer. For a maker, it means the company’s own quantum computers or processors. This does not establish revenue, market share, volumes or future sourcing.

Component roleCUDA-Q, NVQLink and GPU decoding for quantum systems
EvidenceDisclosed: NVIDIA’s NVQLink releases and product page describe the GPU-to-controller architecture, its partners and latency, and Quantinuum’s real-time decoding demonstration.
How we knowDisclosed The company’s own filing, release, annual report, product page or investor record describes the quantum-computing role. Where customers are unnamed, the listing says so.
Primary sourceNVIDIA — supporting disclosure
Company or official disclosure; vendor claims are attributed to their source.
Checked. This is the research review date, not the source publication or quote time.

Keep in perspective

NVIDIA supplies GPUs, networking and software, not qubits or controllers, and does not report quantum revenue. Adopters are mostly research centers and testbeds, and the Helios demonstration used trapped ions rather than superconducting qubits.

Platform business exposure. This describes the breadth or role of the business; it is not an investment rating. A quantum-computing product, design-in or partnership does not by itself establish material quantum revenue, market share, or future returns.

Connections to the assembly

These links explain the technology relationship. The model is illustrative and does not represent an actual manufacturer’s bill of materials.

Decoder & host server

A GPU and CPU server that calibrates the machine, compiles programs and decodes quantum error-correction syndromes in real time.

Scope of the company links: Real-time decoding runs on FPGAs beside the controller or on GPU/CPU hosts. NVIDIA’s NVQLink and CUDA-Q QEC link controllers to GPU servers with round trips under 4 µs, and Quantinuum decoded qLDPC codes in real time on its Helios processor through NVQLink. IBM Quantum designed a Relay-BP decoder prototype on an AMD XCVU19P FPGA (Oct 2025). HPE is integrating quantum processors, controllers and decoders with its Cray supercomputers in research testbeds. Riverlane, whose Deltaflow 2 decoders are integrated with Qblox control hardware, is private.

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