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Intel

Edge AI processors for robot systems

Published by FyncaResearch checked How we research

HUMANOID ROBOT

Where it fits in the robot

Intel and robotics partners have demonstrated physical-AI systems using Core Ultra processors for local perception and control workloads.

What the evidence establishes

Humanoid evidence

Intel names humanoid demonstrations using Core Ultra. This compute exposure does not represent ownership of the spun-out RealSense camera business.

An explicit humanoid product, development program, application, or partnership. This does not establish revenue, market share, or production volumes.

Component roleEdge AI processors for robot systems
EvidenceIntel names humanoid demonstrations using Core Ultra. This compute exposure does not represent ownership of the spun-out RealSense camera business.
Primary sourceIntel — supporting disclosure
Company or official disclosure; vendor claims are attributed to their source.
Checked. This is the research review date, not the source publication or quote time.

Keep in perspective

This entry concerns compute, not ownership of the spun-out RealSense camera business. Other Intel markets remain much larger.

Platform business exposure. This describes the breadth or role of the business; it is not an investment rating. A robotics product or development announcement does not by itself establish material humanoid revenue, market share, or future returns.

Connections to the assembly

These links explain the technology relationship. The model is illustrative and does not represent an actual manufacturer’s bill of materials.

AI & control processor

The main processor executes perception and planning. Real-time control can run on separate processing cores or devices.

Scope of the company links: AI processors and embedded real-time controllers serve different workloads. Arm licenses processor IP; it does not manufacture chips.

AI SERVER RACK

Where it fits in an AI server rack

NVIDIA’s DGX B300 (8 Blackwell Ultra GPUs) uses Intel Xeon 6776P host processors. Under a Sept 18, 2025 agreement Intel will design and manufacture NVIDIA-custom x86 CPUs for NVIDIA’s AI infrastructure platforms, and NVIDIA will invest $5 billion in Intel stock at $23.28 per share. Intel also sells Gaudi 3 AI accelerators with a 32-node Ethernet cluster reference design.

What the evidence establishes

AI-rack evidence

Partner-disclosed: NVIDIA’s DGX B300 page names the Intel Xeon 6776P host CPU, and NVIDIA’s Sept 2025 release describes the custom x86 CPU collaboration.

An explicit AI-server or AI-rack product, design-in, supply role, program, reference design or partnership, such as a part named for rack-scale AI systems or a product sold for AI data centers. For a rack builder, it means the company’s own AI servers or racks. This does not establish revenue, market share, volumes or future sourcing.

Component roleXeon host CPUs for AI servers; Gaudi accelerators
EvidencePartner-disclosed: NVIDIA’s DGX B300 page names the Intel Xeon 6776P host CPU, and NVIDIA’s Sept 2025 release describes the custom x86 CPU collaboration.
How we knowPartner-disclosed A named partner, customer or platform owner’s document names the company. The scope is that document’s product or program, not a general supply relationship.
Primary sourceIntel — supporting disclosure
Company or official disclosure; vendor claims are attributed to their source.
Checked. This is the research review date, not the source publication or quote time.

Keep in perspective

NVL72-class racks use Arm-based Grace or Vera CPUs, not Xeon; Xeon hosts appear in 8-GPU systems such as DGX B300. The NVIDIA-custom x86 CPUs have no disclosed ship date, and Gaudi has no documented rack-scale deployment in the sources captured.

Diversified business exposure. This describes the breadth or role of the business; it is not an investment rating. An AI-server product, design-in or partnership does not by itself establish material AI-rack revenue, market share, or future returns.

Connections to the assembly

These links explain the technology relationship. The model is illustrative and does not represent an actual manufacturer’s bill of materials.

GPU compute dies

Two reticle-sized logic dies joined into one GPU, built on a leading-edge foundry process. They run the matrix math of training and inference. Custom accelerators designed by or for cloud companies are the main alternative.

Scope of the company links: The compute dies. NVIDIA designs Blackwell and Blackwell Ultra (208 billion transistors on two reticle-limited dies, custom TSMC 4NP) and AMD designs the Instinct MI350 and MI455X; NVIDIA discloses that TSMC fabricates Blackwell. Custom accelerators are the alternative: Broadcom co-develops OpenAI-designed accelerators and racks (its other XPU customers are unnamed), Marvell develops custom AI silicon for unnamed customers, and the design-service houses Alchip (an N3 accelerator for a North American cloud provider, from May 2026) and GUC (AI accelerator design support) disclose programs without naming customers. Intel’s Gaudi 3 is a merchant AI accelerator with no documented rack-scale deployment. Hyperscaler chip designers (Google TPU, AWS Trainium) are not mapped because they do not sell the chips as components. Samsung is named as an NVIDIA wafer foundry but not for Blackwell GPU dies, so it is not mapped here.

Host CPU

An Arm-based or x86 processor that runs the operating system, stages data and coordinates the GPUs. In rack-scale designs it shares a coherent high-bandwidth link with its GPUs.

Scope of the company links: NVIDIA’s Grace is the host CPU of GB200/GB300 NVL72: a GB200 rack has 36 Grace CPUs with 2,592 Arm Neoverse V2 cores (NVIDIA spec page). Arm licenses the Neoverse cores; in March 2026 it also launched its own AGI CPU silicon. x86 alternatives are AMD EPYC (18 Venice CPUs in AMD’s Helios rack) and Intel Xeon hosts in 8-GPU HGX-class servers. Montage’s Jintide x86 CPUs have no documented AI-rack role and are not mapped.

QUANTUM COMPUTER

Where it fits in a quantum computer

Released Tunnel Falls (June 15, 2023), a 12-qubit silicon spin chip made on 300 mm wafers in its D1 fab with EUV lithography on a CMOS logic line, and made it available to research labs including LPS and Sandia. Hitachi’s NEDO-backed project (July 22, 2026) will design 100-qubit silicon chips with Intel using Intel’s quantum-device manufacturing processes based on Intel 18A and an Intel qubit process design kit.

What the evidence establishes

Quantum-computing evidence

Disclosed: Intel’s newsroom describes Tunnel Falls and its 300 mm fabrication; Hitachi’s release (partner-disclosed) describes Intel’s 18A-based qubit process and PDK.

An explicit quantum-computing product, design-in, supply role, program or partnership, such as a part sold for quantum computers or a named quantum-computer customer. For a maker, it means the company’s own quantum computers or processors. This does not establish revenue, market share, volumes or future sourcing.

Listed as a quantum-computer maker for its own systems, not as a supplier of the parts inside.

Component roleSilicon spin-qubit chips on 300 mm; 18A-based qubit process
EvidenceDisclosed: Intel’s newsroom describes Tunnel Falls and its 300 mm fabrication; Hitachi’s release (partner-disclosed) describes Intel’s 18A-based qubit process and PDK.
How we knowDisclosed The company’s own filing, release, annual report, product page or investor record describes the quantum-computing role. Where customers are unnamed, the listing says so.
Primary sourceIntel — supporting disclosure
Company or official disclosure; vendor claims are attributed to their source.
Checked. This is the research review date, not the source publication or quote time.

Keep in perspective

Intel sells no quantum computer and its FY2025 10-K does not mention quantum computing; the Hitachi project is R&D running to March 2029. Spin qubits differ from the illustrated transmon chip.

Diversified business exposure. This describes the breadth or role of the business; it is not an investment rating. A quantum-computing product, design-in or partnership does not by itself establish material quantum revenue, market share, or future returns.

Connections to the assembly

These links explain the technology relationship. The model is illustrative and does not represent an actual manufacturer’s bill of materials.

Qubit chip

A silicon die patterned with about a hundred superconducting transmon qubits, the tunable couplers between them and a readout resonator for each. The quantum state lives in these circuits.

Scope of the company links: The qubit die. Makers that design and fabricate their own superconducting chips come first: IBM (Nighthawk links 120 qubits with 218 tunable couplers; wafers made at a 300 mm facility in Albany, where its company Anderon runs a pure-play quantum wafer foundry), Google (105-qubit Willow from its Santa Barbara fab), Rigetti (Fab-1, chiplet-based Cepheus systems, Novera QPUs sold to others), IQM (chips from its own clean room), D-Wave (superconducting annealing QPUs whose wafers SkyWater makes), AWS (the Ocelot cat-qubit prototype) and Fujitsu (a 256-qubit chip co-developed with RIKEN). IonQ is mapped only because it has owned SkyWater, D-Wave’s wafer foundry, since July 31, 2026. GlobalFoundries (a quantum foundry business launched in May 2026 with photonic, ion-trap and spin-qubit partners, developing superconducting processes) and STMicroelectronics (Quobly’s silicon spin-qubit devices in Crolles) are foundries, and Intel’s 12-qubit Tunnel Falls is a silicon spin chip. Trapped-ion, neutral-atom and photonic machines use different hardware and sit under makers. QuantWare, Oxford Quantum Circuits, Quobly and Qolab are private; research fabs such as imec and MIT Lincoln Laboratory are not companies and are not mapped.

Related research

Companies with overlapping sector exposure. Their products and evidence may differ; this is not a list of equivalent investments.

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